Recently, the integration of semiconductor integrated circuits such as LSIs has progressed more and more. In association with this progress in the area of integration, signal input and output operations have accelerated; at the same time, an LSI that employs digital signals, analog signals and DC signals as input and output signals has been developed.
A testing device for an LSI has a plurality of input and output channels each of which is used in accordance with one kind of signal and serves to perform an interface for each of the plural input and output terminals (input and output terminals of digital/analog signals and DC signals as described above) of a device under test (hereinafter referred to as a "DUT").
These input and output channels comprise plural hardware (H/W) modules, and each of these modules is generally operated under time control based on clocks (i.e., clock signals) that are obtained by dividing a single clock, a so-called master clock signal (hereinafter referred to as a "master clock") by an integer number.
Generally, a DUT is divided into plural functional blocks, and some DUTs are frequently operated with plural master clock systems. When these functional blocks are independent of each other, each of the H/W modules of the testing device is operated on the basis of the integer-divided clocks (that is, is operated while the clocks for the respective H/W modules are synchronized with one another) to test each functional block of the device under test. In this manner, a signal environment that substantially corresponds to the environment extant during the real operation of the DUT can be realized.
However, when independence between the functional blocks is low (in other words, when the functional blocks are highly interdependent), the use of signals derived from the integer division of one master clock as described above enables the generation and measurement of only signals having a clock relationship (e.g., frequency) of an integer ratio therebetween, so that there occurs a problem that it is possible only to realize a signal environment which substantially differs from that in the real operation of the DUT. In order to solve this problem, a testing device having two master clock generators which have dependent or independent relationship has been developed. However, a testing device that can simultaneously carry out both a complex control of a signal generation and measurement of each of the H/W modules and a time management thereof has not yet been developed. One of the reasons why such a testing device has not yet been produced resides in the fact that timing adjustment between the modules is carried out through a host computer or by using a special device for timing adjustment.
A known conventional testing device having two independent master clock generators can adjust the timing between the H/W modules only when a testing operation is started. However, in this testing device, the complicated control of the signal generation and measurement cannot be carried out with high accuracy, and the operation timing between the H/W modules operated with different master clocks has a control resolution of only about 1 micro second, and thus the testing device has a problem in reproducing the test timing of a high-speed DUT.
Accordingly, an object of the present invention is to provide a testing device with which an operation similar to a signal generation and measurement operation of a H/W module group operated with a single clock can be realized with at least two independent clock systems. The testing device should be capable of performing both the complicated control of the signal generation and measurement operations, such as realization of time coincidence and arbitrary time difference between events and the time management of the DUT, and should be capable of performing a test of the DUT under an environment closely similar to that extant in the DUT's actual operation, so that reliability of the testing can be improved. The present invention achieves these goals.